Nonvolatile memory device and method of forming the same

ABSTRACT

A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

BACKGROUND

1. Field

Embodiments relate to a nonvolatile semiconductor device and a method offorming the same.

2. Description of the Related Art

Semiconductor devices may be classified into volatile memory devices andnonvolatile memory devices. Volatile memory devices may lose stored datawhen a power supply is interrupted. Nonvolatile memory devices maymaintain stored data even when a power supply is interrupted. Volatilememory devices may include, e.g., a dynamic random access memory (DRAM)device and a static random access memory (SRAM) device. Nonvolatilememory devices may include, e.g., a flash memory device, a phase changememory device, and/or a ferromagnetic memory device. As thesemiconductor industry becomes highly developed, nonvolatile memorydevices having a high integration and a superior characteristic may berequired. Many studies have been performed to satisfy requirements ofusers.

SUMMARY

Embodiments are therefore directed to a nonvolatile semiconductor deviceand a method of forming the same, which substantially overcome one ormore of the drawbacks, limitations, and/or disadvantages of the relatedart.

It is therefore a feature of an embodiment to provide a method offorming a non-volatile memory device that allows for easy control offormation of a multi-element insulating layer.

It is therefore another feature of an embodiment to provide a method offorming a non-volatile memory device that allows for excellent thicknessuniformity in the multi-element insulating layer.

It is therefore another feature of an embodiment to provide anon-volatile memory device optimized for a high level of integration.

It is therefore another feature of an embodiment to provide anon-volatile memory device having superior data retention by minimizingthe amount of bulk traps in the multi-element insulating layer.

At least one of the above and other features and advantages may berealized by providing a method of forming a nonvolatile memory deviceincluding forming a tunnel insulating layer on a substrate, whereinforming the tunnel insulating layer includes forming a multi-elementinsulating layer by a process including sequentially supplying a firstelement source, a second element source, and a third element source tothe substrate, forming a charge storage layer on the tunnel insulatinglayer, forming a blocking insulating layer on the charge storage layer,and forming a control gate electrode on the blocking insulating layer.

One of the first, second, and third element sources may be a siliconsource, another may be a nitrogen source, and the other may be an oxygensource.

The third element source may be the oxygen source and one of the firstand second element sources may be the silicon source and the other maybe the nitrogen source.

The multi-element insulating layer may include a silicon oxynitridelayer, and an oxygen content of the multi-element insulating layer maybe about 30 at. % to about 60 at. %.

Forming the multi-element insulating layer may include performing aplurality of cycles, each cycle including sequentially supplying thefirst element source, the second element source, and the third elementsource to the substrate.

Forming the multi-element insulating layer may include, in sequenceadsorbing the first element source onto the substrate, purging anon-adsorbed first element source, supplying the second element sourceto the substrate to react with the adsorbed first element source,purging an unreacted second element source and a reaction residual,supplying the third element source to the substrate to react with thereacted first and second elements, and purging an unreacted thirdelement source and a reaction residual.

An energy band gap of a bottom surface of the multi-element insulatinglayer may be different from an energy band gap of a top surface of themulti-element insulating layer.

One of the first, second, and third element sources may be a siliconsource, another may be a nitrogen source, and the other may be an oxygensource, forming the multi-element insulating layer may includeperforming a plurality of cycles, each cycle including sequentiallysupplying the first element source, the second element source, and thethird element source to the substrate, and an amount of the oxygensource supplied during the first cycle among the cycles may be differentfrom an amount of the oxygen source supplied during a last cycle amongthe cycles.

The amount of the oxygen source supplied during a first cycle may begreater than the amount of the oxygen source supplied during a lastcycle.

The plurality of cycles may include at least one middle cycle betweenthe first cycle and the last cycle, and an amount of the oxygen sourcesupplied during the middle cycle may be equal to or less than an amountof the oxygen source supplied during a cycle performed just before themiddle cycle.

The amount of the oxygen source supplied during a first cycle may beless than the amount of the oxygen source supplied during a last cycle.

The plurality of cycles may include at least one middle cycle betweenthe first cycle and the last cycle, and an amount of the oxygen sourcesupplied during the middle cycle may be equal to or greater than anamount of the oxygen source supplied during a cycle performed justbefore the middle cycle.

An energy band gap of the multi-element insulating layer may besubstantially uniform.

Forming the tunnel insulating layer may further include forming aninterface layer on the substrate prior to forming the multi-elementinsulating layer, and the multi-element insulating layer may be formedon the interface layer.

The method may further include annealing the multi-element insulatinglayer prior to forming the charge storage layer.

A process gas used in the annealing may include at least one of oxygen,ozone, nitrogen, nitric oxide, nitrous oxide, chlorine, and fluorine.

Forming the multi-element insulating layer may include sequentiallysupplying the first element source to the substrate at a firsttemperature, the second element source to the substrate at a secondtemperature, and the third element source to the substrate at a thirdtemperature.

The first temperature, the second temperature, and the third temperaturemay all be different from each other.

At least one of the above and other features and advantages may also berealized by providing a nonvolatile memory device including a tunnelinsulating layer on a substrate, the tunnel insulating layer including amulti-element insulating layer formed by a process includingsequentially supplying a first element source, a second element source,and a third element source to the substrate, a charge storage layer onthe tunnel insulating layer, a blocking insulating layer on the chargestorage layer, and a control gate electrode on the blocking insulatinglayer.

An energy band gap of a bottom surface of the multi-element insulatinglayer may be different from an energy band gap of a top surface of themulti-element insulating layer.

The multi-element insulating layer may be a silicon oxynitride layer,and an oxygen content of the bottom surface of the multi-elementinsulating layer may be different from an oxygen content of the topsurface of the multi-element insulating layer.

The energy band gap of the multi-element insulating layer may graduallydecrease from the bottom surface of the multi-element insulating layerto the top surface of the multi-element insulating layer.

The energy band gap of the multi-element insulating layer may graduallyincrease from the bottom surface of the multi-element insulating layerto the top surface of the multi-element insulating layer.

An energy band gap of the multi-element insulating layer may besubstantially uniform.

One of the first, second, and third element sources may be a siliconsource, another may be a nitrogen source, and the other may be an oxygensource.

The oxygen content of the multi-element insulating layer may be about 30at. % to about 60 at. %.

The charge storage layer may include an insulating material includingtraps storing charges.

The charge storage layer may include a doped semiconductor material, anda dopant in the charge storage layer may be of the same type as a dopantin a channel region defined in the substrate under the control gateelectrode.

The charge storage layer and the channel region may include p-typedopants.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages will become more apparent tothose of ordinary skill in the art by describing in detail exemplaryembodiments with reference to the attached drawings, in which:

FIGS. 1A, 2A, and 3A illustrate cross sectional views of a method offorming a nonvolatile memory device in accordance with an embodiment;

FIGS. 1B, 2B, and 3B illustrate cross sectional views taken along thelines I-I′ of FIGS. 1A, 2A, and 3A, respectively;

FIG. 4 illustrates a flow chart of a method of forming a multi-elementinsulating layer in accordance with an embodiment;

FIG. 5A illustrates a cross sectional view of a nonvolatile memorydevice in accordance with an embodiment;

FIG. 5B illustrates a cross section view taken along the line II-II′ ofFIG. 5A;

FIG. 6 illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a nonvolatile memory devicein accordance with an embodiment;

FIG. 7A illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a nonvolatile memory devicein accordance with another embodiment;

FIG. 7B illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a modified example of anonvolatile memory device in accordance with the embodiment shown inFIG. 7A;

FIG. 8A illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a nonvolatile memory devicein accordance with still another embodiment;

FIG. 8B illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a modified example of anonvolatile memory device in accordance with the embodiment shown inFIG. 8A;

FIG. 8C illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a nonvolatile memory devicein accordance with further still another embodiment;

FIG. 9A illustrates a top plan view of a NAND type nonvolatile memorydevice in accordance with an embodiment;

FIG. 9B illustrates a cross sectional view taken along the line IV-IV′of FIG. 9A;

FIG. 10A illustrates a top plan view of a NOR type nonvolatile memorydevice in accordance with an embodiment;

FIG. 10B illustrates a cross sectional view taken along the line V-V′ ofFIG. 10A;

FIG. 11 illustrates a block diagram of an electronic system including anonvolatile memory device in accordance with an embodiment; and

FIG. 12 illustrates a block diagram of a memory card including anonvolatile memory device in accordance with an embodiment.

DETAILED DESCRIPTION

Korean Patent Application No. 10-2008-0087868, filed on Sep. 5, 2008, inthe Korean Intellectual Property Office, and entitled: “NonvolatileMemory Device and Methods of Forming the Same,” is incorporated byreference herein in its entirety.

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings; however, they may be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

In the drawing figures, the dimensions of layers and regions may beexaggerated for clarity of illustration. It will also be understood thatwhen a layer or element is referred to as being “on” another layer orsubstrate, it can be directly on the other layer or substrate, orintervening layers may also be present. Further, it will be understoodthat when a layer is referred to as being “under” another layer, it canbe directly under, and one or more intervening layers may also bepresent. In addition, it will also be understood that when a layer isreferred to as being “between” two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent. Like reference numerals refer to like elements throughout.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed itemsand may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc., maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first region/layer could be termeda second region/layer, and, similarly, a second region/layer could betermed a first region/layer without departing from the teachings of thedisclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Embodiments may be described with reference to cross-sectionalillustrations, which are schematic illustrations of idealizedembodiments of the present invention. As such, variations from theshapes of the illustrations, as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, embodimentsshould not be construed as limited to the particular shapes of regionsillustrated herein, but are to include deviations in shapes that resultfrom, e.g., manufacturing. For example, a region illustrated as arectangle may have rounded or curved features. Thus, the regionsillustrated in the figures are schematic in nature and are not intendedto limit the scope illustrated in the embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Spatially relatively terms, such as “beneath,” “below,” “above,”“upper,” “top,” “bottom” and the like, may be used to describe anelement and/or feature's relationship to another element(s) and/orfeature(s) as, for example, illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use and/or operation in additionto the orientation depicted in the figures. For example, when the devicein the figures is turned over, elements described as below and/orbeneath other elements or features would then be oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly. As used herein, “height” refers toa direction that is generally orthogonal to the faces of a substrate.

FIGS. 1A to 3B illustrate cross sectional views of a method of forming anonvolatile memory device in accordance with an embodiment. FIGS. 1B,2B, and 3B illustrate cross sectional views taken along the line I-I′ ofFIGS. 1A, 2A, and 3A respectively.

Referring to FIGS. 1A and 1B, a device isolation pattern 102 may beformed in a semiconductor substrate 100 (hereinafter referred to as a“substrate”) to define an active region. The device isolation pattern102 may be, e.g., a trench type. That is, a trench defining the activeregion may be formed, and the trench may be filled with an insulatingmaterial to form the device isolation pattern 102. The active region maybe a portion of the substrate 100 surrounded by the device isolationpattern 102.

An interface layer 105 may be formed on a portion of the substrate 100including the active region. For example, a thermal oxidation processmay be performed on the portion of the substrate 100 including theactive region to form the interface layer 105. The thermal oxidationprocess for the interface layer 105 may use a process gas including,e.g., oxygen (O₂), nitrous oxide (N₂O), nitric oxide (NO), and/orhydrogen/oxygen (H₂/O₂). The interface layer 105 may be formed on only atop surface of the active region by the thermal oxidation process. Theinterface layer 105 may have a thickness of about 5 Å to about 70 Å. Anitrogen treatment process may be performed on the interface layer 105.Nitrogen may be included in the interface layer 105 by the nitrogentreatment process to form a nitrogen treated interface layer 105.Nitrogen in the nitrogen treated interface layer 105 may accumulate atan interface between the nitrogen treated interface layer 105 and theactive regions and/or at a region near the interface. Bulk traps in theinterface layer 105 and/or traps at the interface between the interfacelayer 105 and the active region may be beneficially minimized by thenitrogen treatment process. The nitrogen treatment process may beperformed using a process gas including, e.g., nitric oxide (NO) and/orammonia (NH₃).

A multi-element insulating layer 110 may be formed on the substrate 100having the interface layer 105. A method of forming the multi-elementinsulating layer 110 will be described referring to the flow chart ofFIG. 4. FIG. 4 illustrates a flow chart of a method of forming amulti-element insulating layer in accordance with an embodiment.

Referring to FIGS. 1A, 1B and 4, a first element source may be suppliedto the substrate 100 (S150). The substrate 100 may be loaded into aprocess chamber and the first element source may be supplied to theprocess chamber to supply the first element source to the substrate 100.The substrate 100 may include the interface layer 105 or the nitrogentreated interface layer 105. The first element source may be a sourceincluding a first element, and may be in a gaseous state. The suppliedfirst element source may adsorb onto the substrate 100. The firstelement source may adsorb onto the interface layer 105 and/or the deviceisolation pattern 102. A portion of the first element source may beadsorbed onto the substrate 100, and another portion of the firstelement source may be not adsorbed to the substrate 100.

A first purging (S155) may be performed on the substrate 100. Thenon-adsorbed portions of the first element source may be removed bypurging. The first purging (S155) may be performed by supplying a firstpurging gas including an inert gas, e.g., argon, to the process chamber.

A second element source may then be supplied to the substrate 100(S160). The second element source may be supplied to the substrate 100by supplying the second element source to the process chamber. Thesecond element source may be a source including a second element, andmay be in a gaseous state. The second element source may react with theportion of the first element source adsorbed onto the substrate in S150.As a result, a first element-second element compound may be formed onthe active region and the device isolation pattern 102. The firstelement-second element compound may be formed on the interface layer105.

A second purging (S165) may then be performed on the substrate 100.Unreacted second element source and/or first reaction residual may bedischarged from the process chamber by the second purging (S165). Thesecond purging (S165) may be performed by supplying a second purging gasincluding an inert gas, e.g., argon, to the process chamber. The firstreaction residual may include, e.g., a residual generated by a reactionof the adsorbed first element source and the supplied second elementsource.

A third element source may then be supplied to the substrate 100 (S170).The third element source may be a source including a third element, andmay be in a gaseous state. The third element source may be supplied tothe substrate 100 by supplying the third element source to the processchamber. The third element source may react with the firstelement-second element compound. As a result, a multi-element insulatinglayer 110 including the first, second, and third elements may be formed.The multi-element insulating layer 110 may be formed on the activeregion and the device isolation pattern 102. The interface layer 105 maybe between the multi-element insulating layer 110 and the active region.One of the first, second, and third element sources may be a siliconsource, another may be a nitrogen source, and the other may be an oxygensource.

After the multi-element insulating layer 110 is formed, a third purging(S175) may be performed the substrate 100. Unreacted third elementsource and/or a second reaction residual may be purged from the processchamber by the third purging (S175). That is, the unreacted thirdelement source and/or the second reaction residual may be removed by thethird purging (S175). The second reaction residual may include, e.g., aresidual generated by a reaction of the first element-second elementcompound and the third element source. The third purging (S175) may beperformed by supplying a third purging gas including an inert gas, e.g.,argon, to the process chamber. The multi-element insulating layer 110may be included in a tunnel insulating layer (120 of FIGS. 2A and 2B).The interface layer 105 may be included in the tunnel insulating layer.

As described above, the multi-element insulating layer 110 may be formedby sequentially supplying the first, second, and third element sourcesto the process chamber housing the substrate 100. Accordingly, anelement content ratio of the multi-element insulating layer 110 may beoptimized. In other words, the element content ratio of themulti-element insulating layer 110 may be substantially uniform, orlocalized element content ratios in the multi-element insulating layer110 may be easily controlled. Also, the multi-element insulating layer110 may have superior thickness uniformity by supplying the first,second, and third element sources in sequence. As a result, themulti-element insulating layer 110 having a superior characteristic maybe embodied. Thus, the tunnel insulating layer (120 of FIGS. 2A and 2B)having a superior characteristic may be embodied.

In a typical insulating layer formed by supplying three kinds of elementsources simultaneously, a characteristic of the insulating layer may bedeteriorated. Reaction temperatures of the three kinds of elementsources may be different from one another, but a process temperature fordepositing the insulating layer may be a maximum temperature among thereaction temperatures of the three kinds of element sources. As aresult, since a reaction rate of one of the element sources ofrelatively low reaction temperature may be increased, it may bedifficult to control the element content ratio of the insulating layer.Also, since it may be difficult to control reaction rates of three kindsof element sources, thickness uniformity of the insulating layer may bedeteriorated.

In particular, if the silicon source, nitrogen source, and oxygen sourceare simultaneously supplied, the nitrogen source having a relatively lowreaction temperature may very actively react due to a high depositionprocess temperature, such that the nitrogen content of the siliconoxynitride layer may become undesirably high. The oxygen content of thesilicon oxynitride layer may thereby become very low. As a result, theoxygen content of the silicon oxynitride layer formed by simultaneouslysupplying silicon, nitride, and oxygen sources may not be greater thanabout 30 at. % (30 atomic %).

However, according to an embodiment, since the multi-element insulatinglayer 110 may be formed by supplying the first, second, and thirdelement sources in sequence, the multi-element insulating layer 110 mayhave superior characteristics and/or superior thickness uniformity.

The steps of S150 to S175 described above may be defined as one cycle.The multi-element insulating layer 110 may be formed by repeatedlyperforming the cycle. The cycle may be repeated until a target thicknessof the multi-element insulating layer 110 is obtained. The elementcontent ratio of the multi-element insulating layer 110 may be veryeasily controlled by controlling the amount of element sources suppliedto the substrate during the cycles.

As described above, one of the first, second, and third element sourcesmay be the silicon source, another may be the nitrogen source, and thethird may be the oxygen source. Accordingly, the multi-elementinsulating layer 110 may include a silicon oxynitride layer. The siliconsource, the nitrogen source, and the oxygen source may be supplied invarious orders. In an implementation, one of the first and secondelement sources may be the silicon source, and the other may be thenitrogen source. The third element source may be the oxygen source. Thesilicon source may include, e.g., a silicon-chlorine compound gas and/ora silicon-hydrogen-chlorine compound gas. In an implementation, thesilicon source may include, e.g., SiH₂Cl₂, SiCl₄, and/or Si₂Cl₆. Thenitrogen source may include, e.g., a NH₃ gas. The oxygen source mayinclude, e.g., O₂, N₂O, and/or NO gas. In an implementation, the siliconsource may include Si₂Cl₆, the nitrogen source may include NH₃, and theoxygen source may include N₂O.

When the multi-element insulating layer 110 is formed by performing aplurality of cycles, the amounts of the silicon, nitrogen, and oxygensources supplied during the cycles may all be equal to one another.Accordingly, in an embodiment, the multi-element insulating layer 110may have substantially uniform contents of silicon, nitrogen, andoxygen. In another embodiment, the silicon, nitrogen, and oxygen contentof the multi-element insulating layer 110 of the multi-elementinsulating layer 110 may be locally controlled by controlling theamounts of element sources supplied during the cycles.

In the case that the multi-element insulating layer 110 includes asilicon oxynitride layer, the oxygen content of the multi-elementinsulating layer 110 may be about 30 at. % to about 60 at. %. Thesilicon content may be about 33.3 at. % to about 42 at. %, and thenitrogen content may be about 6.7 at. % to about 36.7 at. %. The sum ofthe oxygen, nitrogen, and silicon content is 100 at. %. Maintaining theoxygen content in the multi-element insulating layer 110 at about 30 at.% to about 60 at. % may help ensure that bulk traps in the multi-elementinsulating layer 110 are reduced.

According to another embodiment, one of the first, second, and thirdelement sources may be a hafnium source, another may be the siliconsource, and the other may be the oxygen source. Accordingly, themulti-element insulating layer 110 may include a hafnium-silicon oxidelayer.

Referring to FIGS. 2A and 2B, after forming the multi-element insulatinglayer 110, an annealing process may be performed on the multi-elementinsulating layer 110. Bulk traps in the multi-element insulating layer110 may be further reduced by the annealing process. The annealingprocess may be performed using a process gas including, e.g., oxygen(O₂), ozone (O₃), nitrogen (N₂), nitric oxide (NO), nitrous oxide (N₂O),chlorine (Cl), and/or fluorine (F) in the ambient atmosphere.

A capping insulating layer 115 may be formed on the multi-elementinsulating layer 110. The capping insulating layer 115 may be formedduring the annealing process. In an embodiment, when the process gas ofthe annealing process includes a gas containing an oxygen atom, e.g.,oxygen (O₂), ozone (O₃), nitric oxide (NO) and/or nitrous oxide (N₂O),an upper portion of the multi-element insulating layer 110 may oxidizeto form the capping insulating layer 115. In another embodiment, whenthe process gas of the annealing process includes chlorine (Cl) and/orfluorine (F), an upper portion of the multi-element insulating layer 110may be formed into the capping insulating layer 115 containing chlorine(Cl) and/or fluorine (F).

Alternatively, the capping insulating layer 115 may not be formed by theannealing process. For example, the annealing process may be performedat a temperature at which the process gas of the annealing process doesnot react to reduce bulk traps in the multi-element insulating layer110. In this case, the capping insulating layer 115 may be depositedusing, e.g., a chemical vapor deposition (CVD) method or an atomic layerdeposition (ALD) method. The deposited capping insulating layer 115 mayinclude an insulating material having an electron affinity less than anelectron affinity of a portion of the multi-element insulating layer110. The deposited capping insulating layer 115 may include, e.g., asilicon oxide layer.

The tunnel insulating layer 120 may include the interface layer 105, themulti-element insulating layer 110, and the capping insulating layer115. In an implementation, the interface layer 105 and/or the cappinginsulating layer 115 may be omitted.

Referring to FIGS. 3A and 3B, a charge storage layer 125, a blockinginsulating layer 130, and a control gate conductive layer 135 may besequentially formed on the tunnel insulating layer 120. The chargestorage layer 125 may include an insulating material having trapscapable of storing charges. The charge storage layer 125 may include,e.g., silicon nitride and/or nano dots for the traps. The nano dots mayinclude, e.g., a semiconductor and/or a metal, and may be distributed inan insulating material, e.g., an oxide. If the charge storage layer 125includes an insulating material having traps storing charges, the chargestorage layer 125 may be formed on the entire front side of thesubstrate 100 as shown in FIGS. 3A and 3B.

In another embodiment, the charge storage layer 125 may include asemiconductor material being doped with a dopant, e.g., doped silicon,doped germanium, doped silicon-germanium, etc., or an undopedsemiconductor material, e.g., undoped silicon, undoped germanium,undoped silicon-germanium, etc. In these cases, the charge storage layer125 may be formed only on the active region. That is, the charge storagelayer 125 may not be formed on the device isolation pattern 102. Thisallows for a node separation of non volatile memory cells adjacent toone another with respect to the device isolation pattern 102. If thecharge storage layer 125 includes the doped semiconductor material, thedopant in the charge storage layer 125 may be the same type of dopant asin a channel region in the active region. The dopant in the channelregion and the dopant in the charge storage layer 125 may both be ap-type dopant, e.g., boron, etc. Alternatively, the dopant in thechannel region and the dopant in the charge storage layer 125 may bothbe an n-type dopant. Majority carriers generated by the dopant in thecharge storage layer 125 may be of a different type from charges storedin the charge storage layer 125. For example, the majority carriers inthe charge storage layer 125 may be holes, and charges stored in thecharge storage layer 125 may be electrons.

In an implementation, the dopant in the charge storage layer 125 may beof a different type from the dopant in the channel region. For example,one of the dopant in the charge storage layer 125 and the dopant in thechannel region may be an n-type dopant and the other may be a p-typedopant.

The blocking insulating layer 130 may include a high dielectric materialhaving a dielectric constant higher than an oxide and/or the tunnelinsulating layer 120. According to an embodiment, when the tunnelinsulating layer 120 is a multilayer, e.g., interface layer 105,multi-element insulating layer 110, and capping insulating layer 115,the high dielectric material may have a dielectric constant higher thanthe layer of the tunneling insulating layer 120 having the highestdielectric constant. The high dielectric material may include, e.g.,SiN, AlO, Al₂O₃, HfO₂, La₂O₃, HfAl_(x)O_(y), HfAlON, HfSi_(x)O_(y),HfSiON, ZrO₂, ZrSi_(x)O_(y), Ta₂O₃, TiO₂, PZT, PbTiO₃, PbZrO₃, PbO,SrTiO₃, BaTiO₃, V₂O₅, (Ba, Sr)TiO₃ (BST), and/or SrBi₂Ta₂O₉ (SBT).

The control gate conductive layer 135 may be formed of a conductivematerial. According to an embodiment, the control gate conductive layer135 may include a conductive material having a work function of at leastabout 4.0 eV. The control gate conductive layer 135 may include, e.g.,Ti, TiN, TaTi, TaSiN, Ta, W, Hf, HfN, Nb, Mo, RuO₂, RuO, Mo₂N, WN, WSi,Ti₃Al, Ti₂AlN, Pd, Ir, Pt, Co, Cr, CoSi, and/or AlSi. The control gateconductive layer 135 may include a conductive material having a workfunction greater than about 4.0 eV, thereby minimizing the amount ofcharges capable of tunneling through the blocking insulating layer 130from a control gate electrode formed in a subsequent process.Accordingly, program efficiency of a nonvolatile memory device may beimproved.

Referring to FIGS. 5A and 5B, the control gate conductive layer 135 maybe patterned to form a control gate electrode 135a. The control gateconductive layer 135, the blocking insulating layer 130, the chargestorage layer 125, and the tunnel insulating layer 120 may besuccessively patterned. In this case, a tunnel insulating pattern 120a,a charge storage pattern 125a, a blocking insulating pattern 130a andthe control gate electrode 135a may be sequentially formed. The tunnelinsulating pattern 120a may include a sequentially stacked interfacepattern 105a, multi-element insulating pattern 110a, and cappinginsulating pattern 115a.

When the charge storage layer 125 is formed of an insulating materialhaving traps for storing charges, the control gate conductive layer 135may be patterned using the blocking insulating layer 130 as an etchingstop layer to form the control gate electrode 135a. In this case, theblocking insulating layer 130, the charge storage layer 125, and thetunnel insulating layer 120 may extend from both sides of the controlgate electrode 135a.

A source/drain 140 may be disposed in the active region adjacent to bothsides of the control gate electrode 135a. The source/drain 140 may beformed by implanting dopant ions into the active region using thecontrol gate electrode 135a as a mask. In another embodiment, thesource/drain 140 may be an inversion layer generated by a fringeelectric field of the control gate electrode 135a during an operation ofthe nonvolatile memory device.

According to an embodiment described above, the multi-element insulatinglayer 110 in the tunnel insulating layer 120 may be formed on thesubstrate by sequentially supplying the first element source, secondelement source, and third element source to, e.g., the process chamberhousing the substrate. Thus, the element content ratio of themulti-element insulating layer 110 may be easily controlled. Also, themulti-element insulating layer 110 may have superior thicknessuniformity. Consequentially, the tunnel insulating layer 120 may have asuperior characteristic, thereby embodying a nonvolatile memory deviceoptimized for a high level of integration. Also, the nonvolatile memorydevice may have superior reproducibility. In addition, the nonvolatilememory device may have superior data retention by minimizing the amountof bulk traps in the multi-element insulating layer 110.

Next, a nonvolatile memory device according to an embodiment will bedescribed with reference to the drawings. FIG. 5A illustrates a crosssectional view of a nonvolatile memory device in accordance with anembodiment. FIG. 5B illustrates a cross section view taken along theline II-II′ of FIG. 5A.

Referring to FIGS. 5A and 5B, the device isolation pattern 102 definingthe active region may be disposed in the substrate 100, and the tunnelinsulating pattern 120a may be disposed on the active region. The tunnelinsulating pattern 120a may include the multi-element insulating pattern110a. The tunnel insulating pattern 120a may further include theinterface pattern 105a disposed between the multi-element insulatingpattern 110a and the active region, and/or the capping insulatingpattern 115a on the multi-element insulating pattern 110a.

The charge storage pattern 125a may be disposed on the tunnel insulatingpattern 120a. The blocking insulating pattern 130a may be disposed onthe charge storage pattern 125a. The control gate electrode 135a may bedisposed on the blocking insulating pattern 130a. The control gateelectrode 135a may cross the active region. The channel region may bedefined in the active region under the control gate electrode 135a. Thesource/drain 140 may be disposed in the active region at sides of thecontrol gate electrode 135a. The multi-element insulating pattern 110amay extend between the control gate electrode 135a and the deviceisolation pattern 102. The tunnel insulating pattern 120a, the chargestorage pattern 125a, and the blocking insulating pattern 130a mayextend at sides of the control gate electrode 135a to cover thesource/drain 140.

As described above, the multi-element insulating pattern 110a may beformed on the substrate 100 by sequentially supplying the first, second,and third element sources, so that the element content ratio of themulti-element insulating pattern 110a may be efficiently and easilycontrolled.

A nonvolatile memory device according to an embodiment will be describedreferring to an energy band diagram of FIG. 6. FIG. 6 illustrates anenergy band diagram taken along the line III-III′ of FIG. 5A, the energyband diagram illustrating a nonvolatile memory device in accordance withan embodiment. Referring to FIGS. 5A and 6, the energy band diagramrepresents a state of equilibrium. As depicted in FIG. 6, according toan embodiment, the multi-element insulating layer 110a in the tunnelinsulating pattern 120a may have a substantially uniform energy bandgap. Element content ratios of the multi-element insulating pattern 110amay be substantially uniform due to, e.g., sequentially supplying thefirst, second, and third element sources during formation of themulti-element insulating layer 110. Accordingly, the multi-elementinsulating pattern 110a may have a substantially uniform energy bandgap.

An electron affinity of the multi-element insulating pattern 110a may beless than an electron affinity of the charge storage pattern 125a.Accordingly, undesirable leakage of charges stored in the charge storagepattern 125a to the active region due to an electric potential barriergenerated by the multi-element insulating pattern 110a may be minimized.The electron affinity of the multi-element insulating pattern 110a maybe defined by a potential difference between lower edges of a conductionband of the multi-element insulating pattern 110a and a vacuum level.The multi-element insulating pattern 110a may be formed by a methoddescribed with reference to FIGS. 1A, 1B, 2A, and 2B, thereby reducingbulk traps in the multi-element insulating pattern 110a. As a result,undesirable leakage of charges in the charge storage pattern 125a to theactive region through bulk traps in the tunnel insulating pattern 120amay be minimized. Consequently, the nonvolatile memory device mayexhibit superior data retention.

An electron affinity of the interface pattern 105a and/or an electronaffinity of the capping insulating pattern 115a may be less than theelectron affinity of the charge storage pattern 125a. The electronaffinity of the multi-element insulating pattern 110a may be greaterthan the electron affinity of the interface pattern 105a and/or thecapping insulating pattern 115a. In other words, the electron affinityof the multi-element insulating pattern 110a may be greater than theelectron affinities of the interface pattern 105a and/or the cappinginsulating pattern 115a, and less than the electron affinity of thecharge storage pattern 125a. Accordingly, program efficiency may beimproved. For example, during a program operation, charges of thesubstrate 100 may tunnel (e.g., FN tunneling) the tunnel insulatingpattern 120a to be stored in the charge storage pattern 125a. Anelectric potential barrier of the multi-element insulating pattern 110amay be lower than electric potential barriers of the interface pattern105a and/or the capping insulating pattern 110a. Thus, during a programoperation, a tunneling probability of the charges through the tunnelinsulating pattern 120a may increase. As a result, program efficiency ofthe nonvolatile memory device may be improved.

Consequently, program efficiency of the nonvolatile memory device may beimproved together with an improvement of data retention characteristicof the nonvolatile memory device by the multi-element insulating pattern110a. An improvement in program efficiency may result in a nonvolatilememory device having desirably low power consumption.

As described above, the multi-element insulating pattern 110a mayinclude a silicon oxynitride layer. The oxygen content of themulti-element insulating pattern 110a may be about 30 at. % to about 60at. %. Bulk traps in the multi-element insulating pattern 110a may bereduced by a high oxygen content. Also, bulk traps in the multi-elementinsulating pattern 110a may be further reduced by the annealing processdescribed with reference to FIGS. 2A and 2B. As a result, leakage ofcharges through bulk traps of the multi-element insulating pattern 110amay be minimized, thereby improving data retention of the nonvolatilememory device.

An electron affinity of the blocking insulating pattern 130a may be lessthan the electron affinity of the charge storage pattern 125a. Thus,undesirable leakage of charges stored in the charge storage pattern 125athrough the blocking insulating pattern 130a at a data retention nodemay be minimized.

In an embodiment, an energy band gap of the multi-element insulatingpattern 110a may not be uniform. For example, an energy band gap of abottom surface of the multi-element insulating pattern 110a may bedifferent from an energy band gap of a top surface of the multi-elementinsulating pattern 110a. This will be described with reference to thedrawings. FIG. 7A illustrates an energy band gap diagram taken along theline III-III′ of FIG. 5A, the energy band gap diagram illustrating anonvolatile memory device in accordance with another embodiment.

Referring to FIGS. 5A and 7A, the energy band gap of the bottom surfaceof the multi-element insulating pattern 110a may be greater than theenergy band gap of the top surface of the multi-element insulatingpattern 110a. The energy band gap of the multi-element insulatingpattern 110a may gradually decrease from the bottom surface of themulti-element insulating pattern 110a to the top surface of themulti-element insulating pattern 110a. As depicted in FIG. 7A, theenergy band gap of the multi-element insulating pattern 110a maysubstantially linearly decrease. The electron affinity of the bottomsurface of the multi-element insulating pattern 110a may be greater thanthe electron affinity of the interface pattern 105a and/or the cappinginsulating pattern 115a. The electron affinity of the top surface of themulti-element insulating pattern 110a may be less than the electronaffinity of the charge storage pattern 125a.

The multi-element insulating pattern 110a of FIG. 7A may be formed byrepeatedly performing the cycle (S150 through S175) described withreference to FIG. 4. The multi-element insulating pattern 110a of FIG.7A may be formed by varying the amount of at least one element sourcesupplied to, e.g., the process chamber, during the cycles.

The multi-element insulating pattern 110a of FIG. 7A may include asilicon oxynitride layer. In this case, the amount of the oxygen sourcesupplied during the first cycle among the cycles may be larger than theamount of the oxygen source supplied during the last cycle among thecycles. The cycles may include at least one middle cycle between thefirst and last cycles. The amount of the oxygen source supplied duringthe middle cycle may be less than the amount of the oxygen sourcesupplied during a cycle performed just before the middle cycle.Accordingly, as the multi-element insulating pattern 110a approaches thecapping insulating pattern 115a, the oxygen content of the multi-elementinsulating pattern 110a may gradually decrease. As a result, the energyband gap of the multi-element insulating pattern 110a may graduallydecrease. In particular, the energy band gap of the multi-elementinsulating pattern 110a may substantially linearly decrease bydecreasing the amount of the oxygen source supplied to each of thecycles by a specific amount. The oxygen content of the multi-elementinsulating ratio 110a may be about 30 at. % to about 60 at. %. That is,the minimum oxygen content of the multi-element insulating pattern 110amay be equal to or greater than about 30 at. % and less than about 60at. %. The maximum oxygen content ratio of the multi-element insulatingpattern 110a may be equal to or less than about 60 at. % and greaterthan about 30 at. %. The amounts of the silicon source supplied duringthe cycles may be equal to one another. The amounts of the nitrogensource supplied during the cycles may also be equal to one another. Inanother embodiment, the amounts of the silicon source supplied duringthe cycles may be different from one another. The amounts of thenitrogen source supplied during the cycles may also be different fromone another.

According to an embodiment, as depicted in FIG. 7A, an absolute value ofa slope (hereinafter, “slope”) of an upper edge 210 of a valence bandmay be greater than the slope of a lower edge 200 of a conduction bandin the multi-element insulating pattern 110a. That is, the upper edge210 of the valence band may change more steeply than the lower edge 200of the conduction band.

The energy band gap of the multi-element insulating pattern 110a of FIG.7A described above may decrease substantially linearly. In anotherembodiment, the energy band gap of the multi-element insulating pattern110a may decrease in stages, as will be described with reference to thedrawings. FIG. 7B illustrates an energy band diagram taken along theLine III-III′ of FIG. 5A, the energy band diagram showing a modifiedexample of a nonvolatile memory device in accordance with anotherembodiment.

Referring to FIGS. 5A and 7B, as the multi-element insulating pattern110a approaches the capping insulating pattern 115a, the energy band gapof the multi-element insulating pattern 110a may decrease stepwise.

The multi-element insulating pattern 110a of FIG. 7B may be formed byrepeatedly performing the cycle (S150 through S175) described referringto FIG. 4. The cycles may be divided into sub-cycle groups. Each of thesub-cycle groups may include two or more cycles, and the amounts of theelement sources supplied during the cycles in each of the sub-cyclegroups may be equal to one another. The amounts of at least one elementsource supplied during each of the sub-cycle groups may be changed by aspecific amount.

The multi-element insulating pattern 110a of FIG. 7B may include asilicon oxynitride layer. In this case, the amount of the oxygen sourcesupplied during the first sub-cycle group among the sub-cycle groups maybe larger than the amount of the oxygen source supplied during the lastsub-cycle group among the sub-cycle groups. The sub-cycle groups mayinclude at least one middle sub-cycle group between the first and lastsub-cycle groups. The amount of the oxygen source supplied during themiddle sub-cycle group may be less than the amount of the oxygen sourcesupplied during a sub-cycle group performed just before the middlesub-cycle group. Accordingly, as the multi-element insulating pattern110a approaches the capping insulating pattern, the oxygen content ofthe multi-element insulating pattern 110a may decrease stepwise. As aresult, the energy band gap of the multi-element insulating pattern 110amay decrease in stages as depicted in FIG. 7B. The oxygen content of themulti-element insulating ratio 110a of FIG. 7B may be about 30 at. % toabout 60 at. %. The minimum oxygen content of the multi-elementinsulating pattern 110a may be equal to or greater than about 30 at. %and less than about 60 at. %. The maximum oxygen content of themulti-element insulating pattern 110a may be equal to or less than about60 at. % and greater than about 30 at. %. The amounts of the siliconsource supplied during the sub-cycle groups may be equal to one another.The amounts of the nitrogen source supplied during the sub-cycle groupsmay also be equal to one another. In another embodiment, the amounts ofthe silicon source supplied during the sub-cycle groups may be differentfrom one another. The amounts of the nitrogen source supplied during thesub-cycle groups may also be different from one another. Since themulti-element insulating pattern 110a may include a silicon oxynitridelayer, the overall slope of an upper edge 210a of a valance band may begreater than the overall slope of a lower edge 200a of a conduction bandin the multi-element insulating pattern 110a of FIG. 7B.

As described above, according to embodiments illustrated in FIGS. 7A and7B, the energy band gap of the multi-element insulating pattern 110a maydecrease linearly or stepwise. Thus, the multi-element insulatingpattern 110a may include a portion, e.g., a bottom surface, having arelatively high electric potential barrier and another portion, e.g., atop surface, having a relatively low electric potential barrier.Accordingly, programming efficiency may be improved. In other words,when charges of the substrate 100 tunnel the multi-element insulatingpattern 110a, a thickness of a tunneling barrier may be reduced toincrease a tunneling probability of charges.

Also, the upper edge 210 or 210a of the valence band of themulti-element insulating pattern 110a may incline more steeply than thelower edge 200 or 200a of the conduction band of the multi-elementinsulating pattern 110a. Thus, a probability of a hole tunneling themulti-element insulating pattern 110a may increase. As a result, anerasing mechanism of the nonvolatile memory device and/or a writingmechanism may be variously embodied. For example, when charges stored inthe charge storage pattern 125a are electrons, charges of the chargestorage pattern 125a may be discharged to the substrate 100 during anerase operation. Since the probability of a hole tunneling themulti-element insulating pattern 110a increases, holes of the substrate100 may tunnel to the charge storage pattern 125a by way of the tunnelinsulating pattern 100. Accordingly, program efficiency may be improved.

Alternatively, the energy band gap of the bottom surface of themulti-element insulating pattern 110a may be smaller than the energyband gap of the top surface of the multi-element insulating pattern110a. FIG. 8A illustrates an energy band diagram taken along the lineIII-III′ of FIG. 5A, the energy band diagram showing a nonvolatilememory device in accordance with still another embodiment. Referring toFIGS. 5A and 8A, the energy band gap of the bottom surface of themulti-element insulating pattern 110a may be smaller than the energyband gap of the top surface of the multi-element insulating pattern110a. The energy band gap of the multi-element insulating pattern 110amay gradually increase from the bottom surface of the multi-elementinsulating pattern 110a to the top surface of the multi-elementinsulating pattern 110a. As depicted in FIG. 8A, the energy band gap ofthe multi-element insulating pattern 110a may increase substantiallylinearly. The electron affinity (minimum electron affinity) of the topsurface of the multi-element insulating pattern 110a may be greater thanthe electron affinity of the interface pattern 105a and/or the cappinginsulating pattern 115a. The electron affinity (maximum electronaffinity) of the bottom surface of the multi-element insulating pattern110a may be less than the electron affinity of the charge storagepattern 125a.

The multi-element insulating pattern 110a of FIG. 8A may include asilicon oxynitride layer. The multi-element insulating pattern 110a ofFIG. 8A may be formed by repeatedly performing the cycle (S150 throughS175) described referring to FIG. 4. In this case, the amount of theoxygen source supplied during the first cycle among the cycles may beless than the amount of the oxygen source supplied during the last cycleamong the cycles. The cycles may include at least one middle cyclebetween the first and last cycles. The amount of the oxygen sourcesupplied during the middle cycle may be larger than the amount of theoxygen source supplied during a cycle performed just before the middlecycle. Accordingly, as the multi-element insulating pattern 110aapproaches the capping insulating pattern, the oxygen content of themulti-element insulating pattern 110a may gradually increase. As aresult, the energy band gap of the multi-element insulating pattern 110amay gradually increase. In particular, the energy band gap of themulti-element insulating pattern 110a may increase substantiallylinearly by increasing the amount of the oxygen source supplied duringeach of the cycles by the specific amount. The oxygen content of themulti-element insulating pattern 110a may be about 30 at. % to about 60at. %. The minimum oxygen content of the multi-element insulatingpattern 110a may be equal to or greater than about 30 at. % and lessthan about 60 at. %. The maximum oxygen content of the multi-elementinsulating pattern 110a may be equal to or less than about 60 at. % andgreater than about 30 at. %. The amounts of the silicon source suppliedduring the cycles may be equal to one another. The amounts of thenitrogen source supplied during the cycles may also be equal to oneanother. In another embodiment, the amounts of the silicon sourcesupplied during the cycles may be different from one another. Theamounts of the nitrogen source supplied during the cycles may also bedifferent from one another. Since the multi-element insulating pattern110a may include a silicon oxynitride layer, as depicted in FIG. 8A, theslope of the upper edge of the valence band may be greater than theslope of the lower edge of the conduction band in the multi-elementinsulating pattern 110a.

FIG. 8B illustrates an energy band diagram taken along the line III-III′of FIG. 5A, the energy band diagram showing a modified example of anonvolatile memory device in accordance with still another embodiment.Referring to FIGS. 5A and 8B, the energy band gap of the multi-elementinsulating pattern 110a may increase stepwise from the bottom surface ofthe multi-element insulating pattern 110a to the top surface of themulti-element insulating pattern 110a. The multi-element insulatingpattern 110a of FIG. 8B may be formed by repeatedly performing the cycle(S150 through S175) described referring to FIG. 4. The cycles may bedivided into sub-cycle groups. Each of the sub-cycle groups may includetwo or more cycles, and the amount of the element source supplied duringthe cycles in each of the sub-cycle groups may be equal to one another.The amount of at least one element source supplied during the sub-cyclegroups may be changed by the specific amount.

The multi-element insulating pattern 110a of FIG. 8B may include asilicon oxynitride layer. In this case, the amount of the oxygen sourcesupplied during the first sub-cycle group among the sub-cycle groups maybe less than the amount of the oxygen source supplied during the lastsub-cycle group among the sub-cycle groups. The sub-cycle groups mayinclude at least one middle sub-cycle group between the first and lastsub-cycle groups. The amount of the oxygen source supplied during themiddle sub-cycle group may be larger than the amount of the oxygensource supplied during a sub-cycle group performed just before themiddle sub-cycle group. Accordingly, as the multi-element insulatingpattern 110a approaches the capping insulating pattern 115a, the oxygencontent of the multi-element insulating pattern 110a may increasestepwise. As a result, the energy band gap of the multi-elementinsulating pattern 110a may increase in stages as depicted in FIG. 8B.The oxygen content of the multi-element insulating pattern 110a of FIG.8B may be about 30 at. % to about 60 at. %. The minimum oxygen contentof the multi-element insulating pattern 110a may be equal to or greaterthan about 30 at. % and less than about 60 at. %. The maximum oxygencontent of the multi-element insulating pattern 110a may be equal to orless than about 60 at. % and greater than about 30 at. %. The amounts ofthe silicon source supplied during the sub-cycle groups may be equal toone another. The amounts of the nitrogen source supplied during thesub-cycle groups may also be equal to one another. In anotherembodiment, the amounts of the silicon source supplied during thesub-cycle groups may be different from one another. The amounts of thenitrogen source supplied during the sub-cycle groups may also bedifferent from one another. Since the multi-element insulating pattern110a may include a silicon oxynitride layer, the overall slope of anupper edge 260a of a valance band may be greater than the overall slopeof a lower edge 250a of a conduction band in the multi-elementinsulating pattern 110a of FIG. 8B.

The nonvolatile memory devices according to embodiments shown in FIGS.8A and 8B described above may obtain the same beneficial effect as thenonvolatile memory devices described in FIGS. 7A and 7B. In addition, inthe present embodiment, since a relatively high electrical potentialbarrier of the multi-element insulating pattern 110a adjoins the chargestorage pattern 125a, leakage of data stored in the charge storagepattern 125a through the tunnel insulating pattern 120a may be furtherreduced.

Next, according to still another embodiment, the charge storage pattern125a may include a doped semiconductor material. A dopant in the chargestorage pattern 125a and a dopant in the channel region may be of thesame type. This will be described with reference to the drawings. FIG.8C illustrates an energy band diagram taken along the line III-III′ ofFIG. 5A, the energy band diagram showing a nonvolatile memory device inaccordance with still another embodiment.

Referring to FIGS. 5A and 8C, the charge storage pattern 125a mayinclude the doped semiconductor material including the dopant. Thedopant in the charge storage pattern 125a may be the same as the dopantin the channel region under the control gate electrode 135a. Forexample, the charge storage pattern 125a and the channel region may bedoped with p-type dopants. The channel region and the charge storagepattern 125a may be formed of, e.g., p-type silicon. Charges stored inthe charge storage pattern 125a may be electrons. Since the chargestorage pattern 125a may be doped with the p-type dopant, the electronsmay be stored in a valence band of the charge storage pattern 125a.Therefore, a potential barrier for the charges in the charge storagepattern 125a may be generated as a band gap of the charge storagepattern 125a. As a result, data retention of a nonvolatile memory devicemay be improved.

Additionally, holes in the channel region in the substrate 100 may beinjected into the charge storage pattern 125a including the p-type dopedsilicon during an erase operation. That is, electrons in the valenceband of the charge storage pattern 125a may not tunnel through thetunnel insulating pattern 120a via a conduction band of the chargestorage pattern 125a. As described above, the slope of the upper edge210 of the valence band may be greater than the slope of the lower edge200 of the conduction band in the multi-element insulating pattern 110.Therefore, a width of the multi-element insulating pattern 110a tunneledby the holes in the channel region may be decreased. As a result,erasure efficiency of the nonvolatile memory device may be improved.

The multi-element insulating pattern 110a in FIG. 8C may be replacedwith one of the multi-element insulating patterns 110a described withrespect to FIGS. 7B, 8A, and 8B.

Next, a NAND type nonvolatile memory device according to an embodimentwill be described with respect to the drawings. FIG. 9A illustrates atop plan view of a NAND type nonvolatile memory device in accordancewith an embodiment. FIG. 9B illustrates a cross sectional view takenalong the line IV-IV′ of FIG. 9A.

Referring to FIGS. 9A and 9B, a device isolation pattern defining aplurality of active regions (ACT) may be disposed in a substrate. Theactive regions (ACT) may extend in a first direction. The firstdirection may correspond to an x axis direction in FIG. 9A. A stringselection line (SSL) and a ground selection line (GSL), which may besubstantially parallel to each other, may cross the active regions(ACT). The string and ground selection lines (SSL, GSL) may extend in asecond direction substantially perpendicular to the first direction. Thesecond direction may correspond to a y axis direction in FIG. 9A. Aplurality of word lines (WL) may cross the active regions (ACT) betweenthe string selection line (SSL) and the ground selection line (GSL),side by side. The word lines (WL) and the selection lines (SSL, GSL) maybe substantially parallel to one another.

Common drains 140d may be disposed in the active regions (ACT) of a sideof the string selection line (SSL), respectively. Common sources 140smay be disposed in the active regions (ACT) of a side of the groundselection line (GSL), respectively. The common drains 140d and thecommon sources 140s may be regions doped with dopants. A cellsource/drain 140 may be disposed in the active region (ACT) at sides ofeach word line (WL). The cell source/drain 140 may be a region dopedwith a dopant. In another embodiment, the cell source/drain 140 may be,e.g., an inversion layer generated by an edge electric field of the wordline when an operation voltage is applied to the word line (WL).

A bit line contact plug (BC) may be connected to the common drain 140d.A plurality of bit line contact plugs (BC) may be spaced apart from oneanother along the second direction. A common source line (CSL) may bedisposed on a side of the ground selection line (GSL). The common sourceline (CSL) may be electrically connected to the common source 140s. Thecommon source line (CSL) may extend substantially parallel to the groundselection line (GSL) to be electrically connected to the plurality ofsources 140s arranged in the second direction.

Each of the word lines (WL) may include the sequentially stacked chargestorage pattern 125a, blocking insulating pattern 130, and control gateelectrode 135a. The tunnel insulating pattern 120a may be the tunnelinsulating pattern 120a of any embodiment among the embodimentsdescribed above with respect to FIGS. 1 through 8. The charge storagepattern 125a, the blocking insulating pattern 130a, and the control gateelectrode 135a have already been described, and repeated descriptionsthereof are omitted.

The string selection line (SSL) may include a sequentially stacked firstgate insulating layer 190a and a first gate electrode 195a. The groundselection line (GSL) may include a sequentially stacked second gateinsulating layer 190b and a second gate electrode 195b. The first andsecond gate insulating layers 190a and 190b may include the samematerial as the tunnel insulating pattern 120a, the charge storagepattern 125a, and the blocking insulating pattern 130a. In this case,the tunnel insulating pattern 120a may extend to the side to beconnected to the first and second gate insulating layers 190a and 190b.According to an embodiment, the first and second gate insulating layers190a and 190b may include materials different from the tunnel insulatingpattern 120a, the charge storage pattern 125a, and/or the blockinginsulating pattern 130a.

Next, a NOR type nonvolatile memory device according to an embodimentwill be described. FIG. 10A illustrate a top plan view of a NOR typenonvolatile memory device in accordance with another embodiment. FIG.10B illustrates a cross sectional view taken along the line V-V′ of FIG.10A.

Referring to FIGS. 10A and 10B, a device isolation pattern may bedisposed in a substrate 100 to define a first active region (ACT1) and asecond active region (ACT2). A plurality of first active regions (ACT1)may extend in a first direction substantially parallel to one another.The second active region (ACT2) may extend in a second directionsubstantially perpendicular to the first direction. The second activeregion (ACT2) may cross the first active region (ACT1). The firstdirection may correspond to an x axis, and the second direction maycorrespond to a y axis of FIG. 10A. The first and second active regions(ACT1, ACT2) may be a portion of the substrate 100 surrounded by thedevice isolation pattern.

A pair of parallel word lines (WL) may cross the first active region(ACT1). The second active region (ACT2) may be disposed between the pairof word lines (WL). The pair of word lines (WL) may be separated fromthe second active region (ACT2). The pair of word lines (WL) may berespectively included in a pair of NOR type nonvolatile memory cells. Afirst source/drain 140a may be disposed in the first active region ACT1of a side of each of the word lines (WL). A second source/drain 140b maybe disposed in the second active region ACT2 of the other side of eachof the word lines (WL). The second source/drain 140b may be disposedbetween the pair of word lines (WL). The pair of NOR type nonvolatilememory cells may share the second source/drain 140b. The secondsource/drain 140b may extend in the second direction along the secondactive region (ACT2). When the word line (WL) is spaced apart from thesecond active region (ACT2), the second source/drain 140b may extend inthe first active region (ACT1) between the word line (WL) and the secondactive region (ACT2). The first source/drain 140a and the secondsource/drain 140b may be regions doped with dopants. The word line mayinclude the sequentially stacked tunnel insulating pattern 120a, chargestorage pattern 125a, and blocking insulating pattern 130a. The tunnelinsulating pattern 120a may be the same as any one of the embodimentsdescribed above with reference to FIGS. 1 through 8.

An interlayer insulating layer 300 may be disposed on an entire surfaceof the memory device. Bit line contact plugs 310 may penetrate theinterlayer insulating layer 300. The bit line contact plugs 310 may beconnected to the first source/drains 140a, respectively. A bit line (notshown) may be electrically connected to the bit line contact plug 310.The bit line may extend substantially parallel to the first activeregion (ACT1), and may cover an upper portion of the first active region(ACT1). One bit line may be electrically connected to a plurality of thebit line contact plugs 310 connected to the one first active region(ACT1).

According to an embodiment, the nonvolatile memory device describedabove may be included in an electronic system. The electronic systemwill be described in detail with respect to the drawings. FIG. 11illustrates a block diagram representing an electronic system includinga nonvolatile memory device in accordance with an embodiment.

Referring to FIG. 11, an electronic system 1300 may include a controller1310, an input/output device 1320, and a memory device 1330. Thecontroller 1310, the input/output device 1320, and the memory device1330 may be connected to one another through a bus 1350. The bus 1350may be a path through which data may transfer. The controller 1310 mayinclude, e.g., at least one of a microprocessor, a digital signalprocessor, a microcontroller, and/or a logic device having a functionsimilar to the micro processor, the digital signal processor, and themicrocontroller. The input/output device 1320 may include, e.g., akeypad, a keyboard, and/or a display device. The memory device 330 maybe a device storing data. The memory device 1330 may store data and/oran instruction executed by the controller 1310. The memory device 1330may include, e.g., a nonvolatile memory devices according to anembodiment. The electronic system 1300 may further include an interface1340 for transmitting data to a communication network or receiving datafrom a communication network. The interface 1340 may be awireline/wireless shape. The interface 1340 may include an antenna or awireline/wireless transceiver.

The electronic system 1300 may be, e.g., a mobile system, a personalcomputer, an industrial computer, or a logic system performing a varietyof functions. For example, the mobile system may include, e.g., apersonal digital assistant (PDA), a portable computer, a web tablet, amobile phone, a wireless phone, a laptop computer, a memory card, adigital music system, and/or a data transmission/receipt system. Whenthe electronic system 300 is a wireless communication device, theelectronic system 300 may be used in a communication interface protocolof a third generation, e.g., CDMA, GSM, NADC, E-TDMA, CDMA2000, etc.

Next, a memory card according to an embodiment will be described indetail with reference to the drawings. FIG. 12 illustrates a blockdiagram representing a memory card including a nonvolatile memory devicein accordance with an embodiment.

Referring to FIG. 12, a memory card 1400 may include a nonvolatilememory device 1410 and a memory controller 1420. The nonvolatile memorydevice 1410 may store data and may decode the stored data. Thenonvolatile memory device 1410 may include, e.g., a nonvolatile memorydevice according to an embodiment. The memory controller 1420 may outputstored data in response to a request of decoding/writing of a host orcontrol the nonvolatile memory device 1410 to store data.

Exemplary embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation.Accordingly, it will be understood by those of ordinary skill in the artthat various changes in form and details may be made without departingfrom the spirit and scope of the present invention as set forth in thefollowing claims.

What is claimed is:
 1. A method of forming a nonvolatile memory device,comprising: forming a tunnel insulating layer on a substrate, whereinforming the tunnel insulating layer includes forming a multi-elementinsulating layer by a process including loading the substrate in achamber and sequentially supplying a first element source, a secondelement source, and a third element source to the loaded substrate inthe chamber, and the first element source, the second element source,and the third element source are different from one another;, forming acharge storage layer on the tunnel insulating layer; forming a blockinginsulating layer on the charge storage layer; and forming a control gateelectrode on the blocking insulating layer wherein a charge storagelayer, a blocking insulating layer, and a control gate electrode are onthe tunnel insulating layer.
 2. The method as claimed in claim 1,wherein one of the first, second, and third element sources is a siliconsource, another is a nitrogen source, and the other is an oxygen source.3. The method as claimed in claim 2, wherein the third element source isthe oxygen source and one of the first and second element sources is thesilicon source and the other is the nitrogen source.
 4. The method asclaimed in claim 2, wherein: the multi-element insulating layer includesa silicon oxynitride layer, and an oxygen content of the multi-elementinsulating layer is about 30 at. % to about 60 at. %.
 5. The method asclaimed in claim 1, wherein forming the multi-element insulating layerincludes performing a plurality of cycles, each cycle includingsequentially supplying the first element source, the second elementsource, and the third element source to the substrate.
 6. The method asclaimed in claim 1, wherein forming the multi-element insulating layerincludes, in sequence: adsorbing the first element source onto thesubstrate; purging a non-adsorbed first element source; supplying thesecond element source to the substrate to react with the adsorbed firstelement source; purging an unreacted second element source and areaction residual; supplying the third element source to the substrateto react with the reacted first and second elements; and purging anunreacted third element source and a reaction residual.
 7. A method offorming a nonvolatile memory device, comprising: forming a tunnelinsulating layer on a substrate, wherein forming the tunnel insulatinglayer includes: forming a multi-element insulating layer by a processincluding sequentially supplying a first element source, a secondelement source, and a third element source to the substrate, one of thefirst, second, and third element sources is a silicon source, another isa nitrogen source, and the other is an oxygen source; forming themulti-element insulating layer includes performing a plurality ofcycles, each cycle including sequentially supplying the first elementsource, the second element source, and the third element source to thesubstrate; an amount of the oxygen source supplied during the firstcycle among the cycles is different from an amount of the oxygen sourcesupplied during a last cycle among the cycles; and an energy band gap ofa bottom surface of the multi-element insulating layer being differentfrom an energy band gap of a top surface of the multi-element insulatinglayer; forming a charge storage layer on the tunnel insulating layer;forming a blocking insulating layer on the charge storage layer; andforming a control gate electrode on the blocking insulating layer. 8.The method as claimed in claim 7, wherein the amount of the oxygensource supplied during the first cycle is greater than the amount of theoxygen source supplied during the last cycle.
 9. The method as claimedin claim 8, wherein: the plurality of cycles include at least one middlecycle between the first cycle and the last cycle, and an amount of theoxygen source supplied during the middle cycle is equal to or less thanan amount of the oxygen source supplied during a cycle performed justbefore the middle cycle.
 10. The method as claimed in claim 7, whereinthe amount of the oxygen source supplied during the first cycle is lessthan the amount of the oxygen source supplied during the last cycle. 11.The method as claimed in claim 10, wherein: the plurality of cyclesinclude at least one middle cycle between the first cycle and the lastcycle, and an amount of the oxygen source supplied during the middlecycle is equal to or greater than an amount of the oxygen sourcesupplied during a cycle performed just before the middle cycle.
 12. Themethod as claimed in claim 1, wherein: forming the tunnel insulatinglayer further includes forming a nitrogen treated interface layer on thesubstrate prior to forming the multi-element insulating layer, themulti-element insulating layer being formed on the nitrogen treatedinterface layer; and forming the nitrogen treated interface layerincludes performing a thermal oxidation process on the substrate to forman interface layer and performing a nitrogen treatment process on theinterface layer to form the nitrogen treated interface layer.
 13. Themethod as claimed in claim 1, wherein forming the tunnel insulatinglayer further includes forming an interface layer on the substrate priorto forming the multi-element insulating layer, and the multi-elementinsulating layer is formed on the interface layer.
 14. The method asclaimed in claim 1, further comprising annealing the multi-elementinsulating layer prior to forming the charge storage layer.
 15. Themethod as claimed in claim 14, wherein a process gas used in theannealing includes at least one of oxygen, ozone, nitrogen, nitricoxide, nitrous oxide, chlorine, and fluorine.
 16. The method as claimedin claim 1, wherein forming the multi-element insulating layer includessequentially supplying the first element source to the substrate at afirst temperature, the second element source to the substrate at asecond temperature, and the third element source to the substrate at athird temperature.
 17. The method as claimed in claim 16, wherein thefirst temperature, the second temperature, and the third temperature areall different from each other.
 18. The method as claimed in claim 11,wherein an energy band gap of the multi-element insulating layer issubstantially uniform.
 19. The method as claimed in claim 5, wherein:one of the first, second, and third element sources is a silicon source,another is a nitrogen source, and the other is an oxygen source, and anamount of the nitrogen source supplied during the first cycle among theplurality of cycles is substantially equal to an amount of the nitrogensource supplied during the last cycle among the plurality of cycles. 20.The method as claimed in claim 5, wherein: one of the first, second, andthird element sources is a silicon source, another is a nitrogen source,and the other is an oxygen source, and an amount of silicon sourcesupplied during the first cycle among plurality of cycles issubstantially equal to an amount of the silicon source supplied duringthe last cycle among plurality of cycles.
 21. The method as claimed inclaim 5, wherein: one of the first, second, and third element sources isa silicon source, another is a nitrogen source, and the other is anoxygen source, and forming the multi-element insulating layer includeschanging an amount of the oxygen source supplied during each cycle ofthe plurality of cycles by a predetermined amount such that the energyband gap of the multi-element insulating layer substantially linearlydecreases from the bottom surface of the multi-element insulating layerto the top surface of the multi-element insulating layer.
 22. A methodof forming an integrated circuit device, the method comprising: forminga nonvolatile memory device comprising a tunnel insulating layer, acharge storage layer, a blocking insulating layer, and a control gateelectrode by forming the tunnel insulating layer on a substrate, whereinforming the tunnel insulating layer includes forming a multi-elementinsulating layer by a process including loading the substrate in achamber and sequentially supplying a first element source, a secondelement source, and a third element source to the loaded substrate inthe chamber, and the first element source, the second element source,and the third element source are different from one another.
 23. Amethod of forming a nonvolatile memory device, comprising: forming atunnel insulating layer on a substrate, wherein forming the tunnelinsulating layer includes forming a multi-element insulating layer by aprocess including loading the substrate in a chamber and sequentiallysupplying a first element source, a second element source, and a thirdelement source to the loaded substrate in the chamber, and the firstelement source, the second element source, and the third element sourceare different from one another.
 24. The method as claimed in claim 23,further comprising: forming a charge storage layer on the tunnelinsulating layer; forming a blocking insulating layer on the chargestorage layer; and forming a control gate electrode on the blockinginsulating layer.
 25. The method as claimed in claim 1, wherein thesubstrate comprises an active region.